The present invention relates to a semiconductor memory device, and more particularly to a self refresh operation of a semiconductor memory device.
Data stored in a dynamic random access memory (DRAM) eventually fade unlike other semiconductor memory devices such as static random access memory (SRAM) and flash memory. Therefore, the DRAM is required to rewrite the data periodically. The rewriting operation is referred as a refresh operation. The refresh operation is performed by sensing and amplifying cell data and rewriting the amplified cell data at least once during a retention time of the cell data.
There are two operation modes of the refresh operation. The one is an auto refresh mode for performing the refresh operation during an active mode by generating internal addresses in response to an external command. The other is a self refresh mode for performing the refresh operation during a stand-by mode, e.g., a power down mode. The refresh operation is performed by generating the internal address through an internal counter in response to the external command both in the auto refresh mode and in the self refresh mode. The internal address sequentially increases at every input of the external command. Meanwhile, low power DRAMs included in mobile devices such as a portable computer, a personal digital assistant (PDA), and a mobile telephone almost necessarily employ the self refresh mode.
Usually, a refresh period tREF of the self refresh mode is determined by a period signal output from a ring oscillator included in the semiconductor memory device based on a refresh time detected through a test operation. The refresh time is detected row by row. In order to prevent a bit fail, the refresh period tREF is decided according to the row having the shortest refresh time. Herein, the refresh time is defined as the maximum duration of the cell data without the refresh operation.
FIG. 1 is a graph illustrating a bit fail rate according to the refresh time of the semiconductor memory device.
It is assumed that “t1” shown in FIG. 1 is the shortest refresh time of a semiconductor memory device and “t2” shown in FIG. 1 is a normal refresh time of the semiconductor memory device. When the shortest refresh time t1 is selected as the refresh time of the semiconductor memory device, the bit fail rate becomes about 10.sup.-4%. In the meantime, when the normal refresh time t2 is selected as the refresh time of the semiconductor memory device, the bit fail rate becomes about 10.sup.-2%. Therefore, in order to reduce the bit fail the shortest refresh time t1 is selected as the semiconductor memory device. However, when the shortest refresh time t1 becomes the refresh time of the semiconductor memory device, the refresh operation is performed too frequently. In other words, the refresh operation is unnecessarily frequently performed for the rows having the normal refresh time which is longer than the shortest refresh time and, therefore, the current consumption increases.
Meanwhile, a semiconductor memory device employing a dual period self refresh scheme is suggested in order to reduce the current consumption.
FIG. 2 is a block diagram of a conventional semiconductor memory device employing a dual period self refresh scheme.
The semiconductor memory device shown in FIG. 2 stores the refresh time of each row detected through a test operation in a programmable read only memory (PROM) mode register. Then, each cell array block ARRAY BLOCK 0, 1, 2, 3 in the semiconductor memory device selectively uses one of two refresh periods according to the refresh time stored in the PROM mode register and a refresh address A0-A11. The refresh address A0-A11 is generated base on a refresh timer, a internal RAS generator and a address counter. The semiconductor memory device is explained in detail in Dual Period Self Refresh scheme for Low Power DRAM's with On-Chip PROM Mode Register, IEEE JOURNAL OF SOLID STATE CIRCUIT, VOL. 33, No. 2, FEBRUARY 1998. Therefore, the detailed explanation about circuitry and operation thereof will be eliminated. By using the dual period self refresh scheme, the unnecessary current consumption can be reduced. However, the scheme requires the PROM, and it is actually impossible to contain the PROM, which is a non-volatile memory, in the DRAM chip.